Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage nodes, such as trapping layers or other physical phenomena (which is sometimes referred to as writing), determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones, and removable memory modules.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
The memory array is accessed by a row decoder activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the column bit line to the source line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
For some applications, flash memory stores a single bit per cell. Each cell is characterized by a specific threshold voltage, which is sometimes referred to as the Vt level. Within each cell, two or more possible Vt levels exist. These Vt levels are controlled by the amount of charge that is programmed or stored on the floating gate. For some NAND architectures, for example, a memory cell might have a Vt level (e.g., program Vt) greater than zero in a programmed (e.g., logic zero) state and a Vt level (e.g., erase Vt) less than zero in an erase (e.g., logic one) state.
Memory cells are typically programmed using program/erase cycles, e.g., where the memory cells are first erased and subsequently programmed. For a NAND array, a block of memory cells is typically erased by grounding all of the word lines in the block and applying an erase voltage to a semiconductor substrate on which the memory cells are formed, and thus to the channels of the memory cells, to remove the charge from the floating gates. More specifically, the charge is removed through Fowler-Nordheim tunneling of electrons from the floating gate to the channel, resulting in an erase Vt typically less than zero.
Programming typically involves applying a programming voltage to one or more selected word lines and thus to the control gate of each memory cell coupled to the one or more selected word lines, regardless of whether a memory cell is targeted or untargeted for programming. While the programming voltage is applied to the one or more selected word lines, a potential, such as a ground potential, is applied to the substrate, and thus to the channels of these memory cells, to charge the floating gates. More specifically, the floating gates are typically charged through direct injection or Fowler-Nordheim tunneling of electrons from the channel to the floating gate, resulting in a program Vt typically greater than zero.
The mechanism for both programming and erasing results in the passage of electrons though a tunnel dielectric layer, e.g., a tunnel oxide layer, interposed between the substrate and the floating gates of the memory cells, and therefore, electrons can become trapped in the oxide layer. As the number of program/erase cycles increases, an increasing number of electrons become trapped in the oxide layer. The trapped electrons act to increase the charge on the floating gates and thus the program Vt and the erase Vt of the memory cells. Therefore, the program Vt and the erase Vt increase as the number of program/erase cycles increases. As the program Vt and the erase Vt increase with the number of program/erase cycles, the erase voltage applied to the substrate for erasing the memory cells needs to increase to properly erase all the memory cells, and the programming voltage applied to the word lines needs to decrease to avoid over programming the memory cells.
The programming operation typically involves applying, to selected word lines, a number of programming pulses that start at a predetermined starting voltage level, typically insufficient to program all of the targeted memory cells of the selected word lines, and that are incremented until all of the targeted memory cells of the selected word lines are programmed. If the predetermined starting voltage provides for efficient programming when the memory device is new, it may lead to over-programming of some memory cells whose program Vt has increased too much through multiple program/erase cycles. However, if a predetermined starting voltage is chosen to avoid over-programming of memory cells later in the device life-cycle, it will generally lead to inefficient programming when the device is new as an excessive amount of program pulses will be required to program the memory cells.
One or more selected memory cells are typically erased by applying one or more erase pulses having the same or differing (e.g., successively incremented) voltage levels to the substrate while the word line(s) coupled to the one or more selected memory cells are grounded. However, as the number of program/erase cycles increases, it becomes more difficult to erase the memory cells in that the erase threshold voltage increases as the number of program/erase cycles increases, and eventually the memory may not erase. If the erase voltage provides for efficient erase operations when the memory device is new, it will generally lead to inefficient erase operations later in the device life-cycle, as an excessive amount of erase pulses will be required to erase the memory cells whose erase Vt has increased too much through multiple program/erase cycles. However, if the erase voltage is chosen to avoid excessive erase pulses later in the device life-cycle, it may lead to over-erasure of memory cells when the device is new.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative program and erase schemes.